Microelectronics

Welcome to the home page for the Microelectronics Research Aera at Liverpool John Moores University. The group has over 15-years made important contributions in the field of semiconductor reliability, and has gained an international reputation. In the latest UK's official Research Assessment Exercise (RAE) 2008, 60% of the research have been assessed as either being world-class or internationally excellent. Recently completed grant activity is centred on the research and development of new materials and quality assessment for CMOS and Flash memory industry. Issues addressed include interface state generation, oxide degradation and wear out. We have been successful in attracting further EPSRC funding, to investigate the use of new high-k materials in IC fabrication, and to study the stress-induced-leakage-current (SILC) in gate dielectrics in MOS devices. Collaborators include University of Manchester, Liverpool University, Imperial College London, University of Glasgow, International SEMATECH (USA), IMEC (Belgium), NMRC (Ireland), and Università della Calabria (Italy).

Research interests:

High-k gate dielectrics in CMOS process. Reliability of SiO2 gate dielectrics in CMOS devices. VLSI devices and Processing.   Digital/Analogue/Mixed Signal/RF ASIC design. Microelectronic technologies. Image processing.

Members

Full RCEEE Members:

Prof. Jian. F. Zhang (Area leader)

Dr. Weidong Zhang

 
The following is a list of recent additions to our web.

RAE subject success

In the latest UK's official Research Assessment Exercise (RAE) 2008, LJMU is one of the top performing universities in Electrical and Electronic Engineering.

60% of the research in Electrical and Electronic Engineering at LJMU has been assessed as either being world-class (4*) or internationally excellent (3*). 90% of the research was assessed at 2* or above (denoting research of international quality). 
 
Electrical and Electronic Engineering at LJMU  is ranked:

13th against all universities.

1st against all post-92 universities. 

EPSRC Grants for microelectronics research

Professor J Zhang and Dr W Zhang have been awarded a grant of £462,589 from the Engineering and Physical Sciences Research Council (EPSRC) to research High permittivity dielectrics on Ge for end of Roadmap application.

The semiconductor industry is now driven largely by applications pull for mass market consumer goods and it is essential that circuit performance is continually improved if the insatiable demand for such products is to be satisfied. The continuing miniaturisation of transistors within CMOS circuits or 'chips' results in degradation of transport properties in the Si-based MOS transistor channels resulting in reduced drive current and hence circuit speed. It is also increasingly difficult to engineer transistors wherein the ultra-short channel (10s of nanometre) is controlled exclusively by the gate electrode; so-called 'short channel effects'. To control this latter effect, increasingly thin gate dielectric is required (circa 2nm) but this leads to excessive leakage curent through the gate through the quantum mechanical tunnelling effect. This gate leakage compromises the operation of the transistor and most importantly, gives rise to very considerable power consumption which reduces battery lifetime in portable products, and also contributes to severe heating of the chip. The use of a dielectric with a higher permittivity (k) allows for a thicker gate oxide with much reduced leakage, whilst maintaining the drive current of the transistor.

Germanium semiconductor was used for the very first transistors and possesses excellent transport properties, far superior to those of Si. The successful integration of hafnia based dielectrics for the MOS gate stack, first by Intel, closely followed by other major companies, has been instrumental in installing a new radicalism into the industry. Thus there is now considerable interest incorporating a Ge pMOST and either Ge or a III/V material for the nMOST within CMOS gates. The disadvantage of the lack of a good native oxide for the case of Ge is now mitigated by the availability and proven nature of deposited dielectrics. The combination of a high mobility channel made in Ge, and a reliable hi-k gate dielectric, is highly desirable.

The central aim of this project then is to advance the knowledge and underlying science of Ge MOSFETs, crucially in the area of the gate stack. In particular, rare-earth dielectrics on Ge offer the possibility of a 'magic bullet' solution: a fully scaleable gate stack on a high mobility channel, to the end of the CMOS road map dictated by 'Moore's Law.' Hafnia-based gate stacks are at a more advanced stage in the field but require an interfacial layer which calls for further study into the stability of the native oxide (GeO2) and a technological solution for surface passivation. The 'k' can be increased by doping of the hafnia. There is a pressing need to understand the physics underlying the turn-on or threshold voltage of Ge transistors, which is affected by parasitic 'acceptor-like' energy states near the valence band edge and hence find an engineering solution. New measurement techniques need to be developed to assess phenomena peculiar to Ge devices. Furthermore, the reliability has hardly been looked at for Ge oxide stacks. There are certainly a radically different set of issues compared to Si which will have, in turn, an impact on the suitable materials in the gate stack. Interface states near the conduction band edge are thought to be responsible for the low electron mobility which is proving a 'killer' for the nMOST.

These technological challenges will be addressed in this project, by a team who have individually and collaboratively, had active participation in dielectrics research over a period of decades. The team cover the subject from atomistic level theory and modelling, through screening of novel materials and chemical precursors, growth and deposition, fabrication, physical and electronic characterisation; to reliability testing. The group members have very strong links into industry and research institutions along this chain of expertise.

The Engineering and Physical Sciences Research Council (EPSRC) have awarded a three-year research grant of £191K to Professor Jian Zhang for a project, which aims to search for and evaluate new materials for nano-meter transistors.

Dr. Weidong Zhang has been awarded a three-year research grant of £123K by the Engineering and Physical Sciences Research Council (EPSRC), which will investigate and evaluate the Stress-Induced-leakage-current (SILC )in gate oxides of MOS devices.
 
 
The microelectronics-led revolution drives the development of many everyday electronic products, such as personal computers, mobile phones, and digital cameras.

The performance and price of these products depends upon the ability of microchip manufacturers to be able to place more and more devices on a single chip. However, the production of ever-smaller devices presents significant challenges. Unless new materials and devices are found to enable the development of device sizes within the nano-meter range, the microelectronic revolution could end in 5-10 years. The new grants will enable us to carry out in-depth research in this challenging field.

The group has a partnership with Liverpool University and University of Manchester, and involves collaboration with leading research and industrial organisations both in USA and in Europe. The School of Engineering has strongly supported the development of research in this important area with significant impact on undergraduate and post-graduate programmes.