Projects
J. F. Zhang, "Performance, degradation and defect structure of MOS devices using high-k materials as gate dielectrics," sponsored by EPSRC.
Parnters: Imperial College London, University of Glasgow, International SEMATECH, IMEC, NMRC.
Start: 2005. End: 2008
Abstract:
The transistors in integrated circuits have increased in speed and reduced in cost and power consumption because of reduced transistor size in successive technology generations. However, it is not possible to reduce the voltage to the same scaling factors so the electric fields have increased. The silicon dioxide which is used as the gate of these transistors is now so thin that a significant current flows through it because of direct tunnelling. This increases power consumption and reduces reliability. Future transistor generations will need a gate dielectric of higher permittivity (high-k) so allowing a larger physical thickness of dielectric to be used without increasing the equivalent electrical thickness. This is the most important single issue facing the development of a key IT technology and one in which new ideas and approaches to measurement are required. The proposed high-k materials (materials based on hafnium oxide will be studied initially) are physically and chemically very different to silicon dioxide. Considering the importance of this technological leap surprisingly little is known about their interface characteristics with silicon or about the trapping sites in the oxide. In this research programme we will collaborate with IMEC in Belgium, SEMATECH in the USA, NMRC in Ireland and Glasgow University to achieve an understanding of the underlying science of these dielectrics. This will be done by applying both novel research tools and industry standard methods to analyse the interface and bulk trapping centres and to observe their evolution under electrical stress. A key issue will be the role of hydrogen and deuterium in these materials and the physical and electronic structure of the traps.
W. D. Zhang, "Stress-Induced Leakage Current (SILC) in Thin Gate Oxides of MOSFETs," Sponsored by EPSRC.
Start: 2005. End: 2008
Abstract:
The feature size of Metal-Oxide-Semiconductor (MOS) transistors, which is the most important active element in integrated circuit (IC) technology, has kept scaling down aggressively in recent years. The thickness of its gate oxide is one of the key parameters rapidly approaching its fundamental limit, resulting in serious concerns about its reliability and lifetime prediction. The Stress-Induced Leakage Current (SILC) has been used to characterise the degradation of ultra-thin gate oxides and to predict their breakdown and lifetime, as it is generally believed that SILC is caused by defects generated in gate oxides. However, the mechanism of the SILC is still not clear, since much less attention has been paid to investigating the relation between the SILC and defect generation in the oxide, especially how the defect can act as a step-stone for the SILC. The latest results from IBM suggested that the SILC measurements might not be used as a reliable measure of the critical defect density. The applicant's recent results also indicate a complicated relation between the generated defects and the SILC. The objective of this research is to carry out an in-depth investigation on the SILC generation and its relation with defect generation, and to assess its impact on the oxide breakdown prediction. This will provide important information to the quality assessment, reliability and modeling sections of the IC industry. The most important outcome of this research will be the potential improvement in the IC reliability assessment techniques.
J. F. Zhang, "Hole Trap Generation and It's Role In Oxide Breakdown", sponsored by EPSRC.
Parnters: Magneto-Electronics, Imec.
Start: 2001. End: 2004
Abstract:
The recent work of IBM researchers shows that the maximum operation voltage for future generation of CMOS technology will not be able to follow the roadmap defined by the Semiconductor Industry Association (SIA), because of the gate oxide breakdown, recently. The most successful model is developed by IMEC and IBM and is based on electron trap generation in the oxide. However, difficulties have been encountered when this model is applied to the latest results. In this model, the contribution of hole trap generation to the breakdown has not been considered, since there is little information available on hole trap creation. The recent preliminary results of the applicant show that a large amount of hole traps can be created. The objective of this programme is to carry out a systematic and focused investigation in hole trap generation and its role in oxide breakdown. The issues to be addressed include the hole trapping kinetics, effects of temperature, hydrogen and nitration on hole trap generation, and the contribution of hole trap generation to breakdown. The prime researchers at both IMEC and IBM consider the proposed research to be important and timely.
J. F. Zhang, "THE POST-STRESS DEGRADATION OF MOS DEVICES," sponsored by EPSRC.
Parnters: Magneto-Electronics, Imec, GEC Plessey Semiconductors.
Start: 1997. End: 2001
Abstract:
The stress induced device degradation is one of the main factors limiting the operation voltage and speed of MOS circuits. Degradation can occur not only during the stress, but also after the stress is terminated. There is little information available on the post-stress degradation and the current understanding of it is poor. The aim of this research proposal is to carry out a systematic investigation on the post-stress degradation. It will start with establishing the dependence of post-stress degradation on key experimental parameters, such as temperature and electrical field strength. Efforts will then be made to model the dynamic behaviour of the post-stress degradation. The physical mechanism will be studied and the origin of the instability will be explored. Based on the above information, the impact of post-stress degradation on device lifetime will be assessed. The whole programme will be carried out in collaboration with industry and research centres, which are developing advanced CMOS processes.
